The disclosures herein relate generally to processors, and more specifically, to processors that employ issue queues with instruction age tracking management.
Modern information handling systems (IHSs) often execute instructions out-of-order to achieve greater processing efficiency. Because out-of-order instruction handling is common in modern IHSs, processors typically track the dependency characteristics between instructions in an instruction issue queue. Another characteristic that processors track for instructions in an issue queue is the age of the instructions. The instruction age corresponds to the dispatch order that a particular instruction exhibits in an issue queue relative to other instructions of that issue queue. For example, the last instruction to dispatch to an issue queue is known at the youngest instruction in that issue queue. Alternatively, the oldest instruction residing in an issue queue is the oldest instruction of that issue queue relative to all other instructions of that issue queue.
Many issue queues maintain or store a relative age from oldest through youngest for all instructions that the issue queue stores. The age of a particular instruction is one of multiple characteristics that an issue queue may maintain or store for that particular instruction. For example, a particular instruction may not issue from the issue queue until dependencies for that particular instruction are met. These dependencies may include, data dependencies, address dependencies, and other dependencies. A processor may select the oldest instruction to issue to an execution unit when the processor determines that dependencies for that particular instruction are met. That particular instruction may issue to an execution unit within the processor for further processing.
An issue queue may employ an age matrix to manage age data for each instruction within that issue queue. An age matrix is a matrix or array of data that determines each instructions relative age or dispatch order relative to other instructions within an issue queue. An issue queue may update the age matrix data during the issue of any particular instruction to an execution unit, or upon the dispatch of any new instruction into the issue queue. An issue queue age matrix may update latches or other memory cell data to maintain instruction age information. Updating latches within an age matrix may require latch clocking and the consumption of important processor power resources. Processor power resources may be of particular concern to IC designers and other entities.